Project Frankenstein: Volume XXII

SCSI Bus Reset & Hardware Exception Handling

This volume details the low-level stability mechanisms of the Hitachi-LG GCC-4241N. It focuses on the drive's response to the SCSI Bus Reset (RST) signal and the CPU's internal Hardware Exception vectors. Mastering these is essential for maintaining persistent authentication states and diagnosing "silent crashes" during hybrid development [cite: User Summary, Volume XV: Dispatcher Tables, pp_win.c].

1. The SCSI Bus Reset (RST)

The SCSI Bus Reset is a physical signal that forces all devices on the bus to clear their current command queue and return to a known idle state [cite: Volume XVIII: SCSI Bus Controller]. On the original Xbox, this occurs during every cold boot and soft reboot [cite: User Summary].

Component	VMA / Offset	Behavior upon RST
RST Interrupt Vector	`0x00000010`	Jumps to the native bus-reset handler [cite: Volume XV: Dispatcher Tables].
SRAM State	`0x40000000+`	Natively, the reset handler clears many SRAM flags, including the authentication state [cite: User Summary].
SCSI Registers	`0x9000D000+`	The SBC_CTRL register is re-initialized to standard IDLE [cite: Volume XVIII: SCSI Bus Controller].

The Persistence Problem

Because the native reset handler clears SRAM, the Media Authorized Flag at 0x2CC is lost [cite: Project_Frankenstein_Vol_VI_Addendum.html, 129_perfect_trampoline_v18.py]. To prevent the console from rejecting a disc after a soft reboot, the RAM Cave must hook the RST vector to skip the zeroing of critical hybrid flags [cite: 129_perfect_trampoline_v18.py].

2. Hardware Exception Vectors

When the MN103S CPU encounters an error it cannot handle—such as an illegal instruction or an address alignment error—it jumps to a specific "Panic" vector [cite: User Summary].

Exception Type	Vector Address	Common Trigger in Frankenstein
NMI (Non-Maskable)	`0x00000002`	Critical hardware failure or manual debug break.
Address Error	`0x00000004`	DMA Misalignment: Attempting to move data to a non-word boundary [cite: Volume XVI: DMA Controller].
Illegal Instruction	`0x00000006`	Executing corrupted code in the RAM Cave or a failed Poke [cite: pp_win.c, Volume XXI: DRAM Boundaries].

3. The Diagnostic "Black Box" (SRAM)

When a crash occurs, the MN103S saves the state of the registers into a specific SRAM scratchpad before halting [cite: User Summary]. By using the pp_win Peek tool, the developer can extract this "Black Box" data for post-mortem analysis [cite: pp_win.c].

Diagnostic Byte	SRAM Address	Description
Exception Cause	`0x40000AF0`	Code indicating which vector was triggered.
Program Counter (PC)	`0x40000AF4`	The exact memory address of the instruction that caused the crash.

4. Implementing the RST Persistence Hook

To ensure the hybrid firmware remains stable during Xbox reboots, the following assembly is used to "protect" our SRAM state [cite: 129_perfect_trampoline_v18.py].

; MN103S Assembly: RST Hook for Persistence
; Target: Vector 0x00000010
RST_Persistence_Hook:
    mov     (0x2CC, a1), d0  ; Save current Auth Flag [cite: Project_Frankenstein_Vol_VI_Addendum.html]
    call    Native_RST_Code  ; Run native cleanup
    mov     d0, (0x2CC, a1)  ; Restore Auth Flag
    ret