Project Frankenstein: Volume XXIII

Cache Controller & Coherency Management

This volume provides the technical specification for the internal Cache Controller and associated control registers of the Matsushita MN103S CPU in the LG/Hitachi GCC-4241N. Mastering cache coherency is essential for "Poke" operations, ensuring that patched code in RAM is correctly synchronized and executable by the instruction pipeline [cite: User Summary, pp_win.c].

1. The MN103S Split-Cache Architecture

The MN103S utilizes a split Harvard-style cache to maximize throughput. This architectural separation creates a specific challenge for code injection: the I-D Coherency Gap [cite: User Summary].

Instruction Cache (I-Cache): Stores pre-fetched machine code instructions. Natively, this is read-only [cite: User Summary].
Data Cache (D-Cache): Stores data reads and writes. Your Poke operations write to this cache, not directly to RAM [cite: User Summary, pp_win.c].

2. Cache Control Registers (VMA)

The cache is controlled through memory-mapped registers in the high peripheral space [cite: User Summary].

Register Name	Address (VMA)	Description / Hybrid Usage
`CHCTR`	`0x90000000`	Global Control: Enables/Disables I and D caches. Used to trigger bulk flushes [cite: User Summary].
`DCACHE_FLG`	`0x90000004`	Flush Trigger: Forces the D-Cache to write its dirty lines back to physical SDRAM [cite: User Summary].
`ICACHE_INV`	`0x90000008`	Invalidate Trigger: Clears the I-Cache, forcing a re-fetch of the current VMA [cite: User Summary].

3. The "Poke-to-Execute" Workflow

Theory: Closing the Coherency Gap

When you use pp_win.exe to patch a live drive, the new instructions are trapped in the D-Cache. If the CPU jumps to that address immediately, it will read stale data from the I-Cache and crash [cite: pp_win.c]. You must follow this sequence:

Write (Poke): Payload enters D-Cache [cite: pp_win.c].
Flush (D-Cache): Data moves from D-Cache to Physical RAM [cite: User Summary].
Invalidate (I-Cache): CPU clears its instruction buffer [cite: User Summary].
Execute (Jump): CPU fetches fresh instructions from Physical RAM [cite: pp_win.c].

4. MN103S Assembly: Coherency Synchronization

This assembly routine should be executed within the RAM Cave or triggered via Mode Select ($55) before jumping to a new patch [cite: 129_perfect_trampoline_v18.py, pp_win.c].

; MN103S Assembly: Global Cache Sync
; Target: SRAM Cave 0x40008A00
Sync_Cache:
    mov     0x90000000, a0  ; Point to CHCTR
    mov     0x0000000C, d0  ; Logic Bits: Flush D + Inval I
    mov     d0, (a0)        ; Trigger hardware sync
    
    ; Pipeline Safety Delay
    nop
    nop
    nop
    ret                     ; Coherency established