## Panasonic MN103S: Port Initialization Matrix

Extracted from Boot Vector (Offset `0x000000` block). This matrix defines the initial hardware state of the I/O pins before the drive engages the spindle or laser.

Port/SFR Base (Hex) | Initialization Value | Binary Pin Mask (Pins 7 → 0) | Inferred Pin Configuration
--- | --- | --- | ---
03 10 | 02 00 | 00000010 00000000 | Mixed State (Pin 1 Output, remainder Input)
03 14 | 80 10 | 10000000 00010000 | Mixed State (Pins 7 and 4 Configured)
02 04 | 00 | 00000000 | All Pins Input (Read-Only)
03 40 | 00 | 00000000 | All Pins Input (Read-Only)
02 30 | FC CC FF FF 00 00 | 11111100 11001100 ... | Complex Block Initialization (Likely Memory/Bus config)
03 44 | 2C 90 | 00101100 10010000 | Mixed State (Pins 2, 3, 5, 7 Configured)
02 34 | 00 | 00000000 | All Pins Input (Read-Only)
03 70 | 80 14 | 10000000 00010100 | Mixed State (Pins 2, 4, 7 Configured)
02 60 | 00 | 00000000 | All Pins Input (Read-Only)
03 74 | 80 14 | 10000000 00010100 | Mixed State (Pins 2, 4, 7 Configured)
02 64 | F0 FC FF ... | 11110000 11111100 ... | Heavy Output Configuration (Likely Motor/Stepper drives)

* Note: In Panasonic MN103 architecture, a binary '0' in the Direction Register configures the pin as an Input (High-Z), while a '1' configures it as an Output (Drive High/Low).