# Project Frankenstein: Volume XVIII

## SCSI Bus Controller (SBC) Registers

This volume provides the register-level mapping for the integrated SCSI Bus Controller (SBC) within the Matsushita MN103S processor of the GCC-4241N. Understanding these registers is vital for manual phase management, bus arbitration, and diagnosing communication desynchronization during the Ignition phase of firmware deployment [cite: User Summary, gcc_hitachi_flasher.c, pp_win.c].

## 1. SBC Hardware Architecture

The SBC handles the physical layer and protocol timing of the ATAPI/SCSI bus. It manages the transitions between Command, Data, Status, and Message phases automatically, but provides manual overrides via the peripheral I/O space [cite: User Summary].

### Theory: The CDB Cache

When an SBC IRQ (Interrupt `0x00000010`) occurs, the hardware has already moved the incoming Command Descriptor Block into the internal SRAM cache [cite: Volume XV: Dispatcher Tables]. For the 4241N, this cache is mapped to `0x40000840` [cite: 129_perfect_trampoline_v18.py].

## 2. SCSI Controller Register Map

These registers are memory-mapped in the high peripheral VMA range of the MN103S [cite: User Summary].

Register | Typical VMA | Description
--- | --- | ---
`SBC_DATA` | `0x9000D000` | Data FIFO: Direct access to the 8-byte/16-byte SCSI data buffer.
`SBC_STAT` | `0x9000D004` | Status Register: Indicates current bus phase and IRQ pending status.
`SBC_CTRL` | `0x9000D008` | Control Register: Used to manually set bus phases or reset the interface.
`SBC_CDB_LEN` | `0x9000D00C` | CDB Size: Tracks if the current command is 6, 10, or 12 bytes [cite: gcc_hitachi_flasher.c].

## 3. Phase Management & Diagnostic Overrides

In certain "Frankenstein" scenarios—such as jumping to RAM while the bus is active—the drive may become desynchronized from the Windows Host [cite: gcc_hitachi_flasher.c]. Manual phase manipulation via `SBC_CTRL` can force the drive to send a Status GOOD packet even if the native logic has halted [cite: Volume XIII: Error Dispatcher Mapping].

### Manual Status Delivery (Pseudo-Code)

    void Force_SCSI_Status_Good() {
        // 1. Manually set phase to STATUS (0x03)
        Set_Register(0x9000D008, 0x03);

        // 2. Load 'GOOD' Status (0x00) into FIFO
        Set_Register(0x9000D000, 0x00); [cite: Volume XIII: Error Dispatcher Mapping]

        // 3. Manually set phase to MESSAGE IN (0x07)
        Set_Register(0x9000D008, 0x07);

        // 4. Send COMMAND COMPLETE (0x00)
        Set_Register(0x9000D000, 0x00);
    }

## 4. Bus Controller Interaction with SRAM

The SBC interacts with the following SRAM locations to maintain state during Peek & Poke operations [cite: pp_win.c, Volume VI: Memory & Buffer Map].

- CDB Cache: `0x40000840` (12 bytes) [cite: 129_perfect_trampoline_v18.py].
- Status Flag: `0x40000A08` (SCSI Status to be returned) [cite: Volume XIII: Error Dispatcher Mapping].
- Sense Buffer: `0x40000A10` (18-byte Sense Data packet) [cite: Volume XIII: Error Dispatcher Mapping].

### Diagnostic Warning: Bus Timeout

The Windows `SPTD` layer expects a response within the `TimeOutValue` (e.g., 15-60 seconds) [cite: gcc_hitachi_flasher.c, pp_win.c]. If your RAM Cave payload enters an infinite loop without updating the `SBC_STAT` or delivering a phase change, the Host will drop the bus, necessitating a hardware power-cycle [cite: gcc_hitachi_flasher.c].