# Batch 04 Primary Evidence Summary

## Sources and hashes

| Source | Size | SHA-256 |
|---|---:|---|
| GCC-4241N service manual | 914254 | `2cee512bcbe50e5c00548c647fcf04aa70a835ba5f1bb1afbfdc82200a8bd43b` |
| MN103S Instruction Set | 1041705 | `a0d9d14e059aafa36b2b41281a8e767352baaced27898184e510b7e931c00824` |
| Panasonic MN103S User Manual | 3315232 | `d2475920c5b9da76609a824a17391808382ccc42030f218bf67fabbfbb010f1c` |
| SCSI-3 command set | 4939067 | `b96b41ff1b17b7ab47f23d95c4ac997d7a7365f34f2d5d0e43b8df98582219b2` |

## Evidence used

The GCC-4241N service manual provides primary hardware evidence that:

- the drive uses an MN103S63G-class controller with an ATAPI interface;
- the controller block contains DMA and DMA-interface blocks;
- the drive has 2 MB external SDRAM and 512 KB flash;
- the drive uses a BH6590KU motor/actuator/stepping/tray driver.

The MN103S instruction documentation confirms:

- a 32-bit architecture with D0-D3 data registers and A0-A3 address registers;
- the listed MOV, MOVBU, MOVHU, CMP, BTST, BSET, BCLR, JMP, CALL/CALLS,
  RET/RETS, and branch instruction families;
- BTST/BSET/BCLR immediate operands are masks, not human bit numbers;
- the reset-vector location is architecture/product-map dependent and is not
  the historical fixed table of offsets 0x00, 0x08, 0x10, and 0x18.

The Panasonic user manual confirms for the documented MN103S product family:

- reset execution begins at 0x40000000;
- NMI begins at 0x40000008;
- level interrupts branch through programmable interrupt-vector address
  registers, rather than fixed timer/SCSI/tray slots at 0x08/0x10/0x18.

The SCSI command-set specification confirms:

- status 0x02 is CHECK CONDITION;
- sense key 0x05 is ILLEGAL REQUEST;
- ASC/ASCQ 0x21/0x00 is LOGICAL BLOCK ADDRESS OUT OF RANGE;
- ASC/ASCQ 0x24/0x00 is INVALID FIELD IN CDB;
- ASC/ASCQ 0x04/0x01 is LOGICAL UNIT NOT READY, BECOMING READY.

Current GCC-4241N A101 analysis provides generated, non-hardware evidence that:

- normalized firmware addresses use a 0x90000000 ROM base;
- 0x10C80000 is detected as a DRAM staging buffer;
- firmware contains repeated accesses to low address 0x2CC;
- current handler candidates differ substantially from the historical
  0x721E6/0x7222E/0x72266/0x27198 tables.

The generated analyzer output is treated as partially corroborating evidence,
not as primary hardware proof.
