# Volume XXVIII: The MN103S63G Hardware Map

This document details the verified physical pinouts and logical port mappings for the Panasonic MN103S63G processor on the GCC-4241N hardware, specific to the optical drive's tray and status I/O.

## Hardware I/O Pin Map

Component | Physical Pin | Logical Port / SFR | Action / Trigger
--- | --- | --- | ---
Tray Closed Switch (Back) | 184 / 173 | `P13` (Port 1, Bit 3 - multiplexed with TX/P18) | When the tray closes, it flips this bit.
Tray Open Switch (Front) | 192 / 181 | `MONI7` (multiplexed with NTRYCL) | When the tray fully ejects, it flips this bit.
Eject Button | 190 / 179 | `MONI5` (multiplexed with DASPST) | Pressing the button flips this bit.
Activity LED | 237 / 223 | `P0` (Port 0, multiplexed with SERIAL) | Driving this bit High/Low triggers the transistor base, lighting the LED.