# Project Frankenstein: Volume XXI

## DRAM Buffer Boundaries & Memory Protections

This volume provides the technical specification for the physical and logical boundaries of the external SDRAM in the LG/Hitachi GCC-4241N. Defining these "No-Fly Zones" is critical for preventing the firmware accumulation buffer from corrupting injected hybrid logic during live development and flashing [cite: User Summary, Volume VI: Memory & Buffer Map].

## 1. The 512KB Accumulation Wall

During the Windows Flashing Routine, the host streams exactly 524,288 bytes (512KB) into the drive's memory [cite: gcc_hitachi_flasher.c]. This data is staged in SDRAM Buffer A [cite: Volume VI: Memory & Buffer Map].

Region | VMA Range | Description
--- | --- | ---
Start of Buffer | `0x10C80000` | Initial block (Sequence 0xFF) write point [cite: gcc_hitachi_flasher.c, Volume VI: Memory & Buffer Map].
The Wall (Limit) | `0x10D00000` | Absolute termination of the 512KB firmware image [cite: gcc_hitachi_flasher.c, Volume VI: Memory & Buffer Map].

### Critical Risk: Buffer Overrun

If a manual `Poke` operation or a malformed flasher write extends beyond `0x10D00000`, the drive will overwrite the Stack Pointer or Peripheral I/O space [cite: pp_win.c]. This results in an immediate hardware exception and a "Silent Brick" where the drive stops responding to the SCSI bus [cite: Volume XVIII: SCSI Bus Controller].

## 2. Memory Mirroring & DMA Safety

The MN103S CPU mirrors memory regions to simplify addressing, but these mirrors are not all DMA-capable [cite: User Summary].

- Standard Data Range: Always use the `0x10xxxxxx` range for large data buffers (SDRAM) [cite: Volume VI: Memory & Buffer Map].
- DMA Constraint: The DMA Controller is hardwired to specific physical address ranges. Attempting a DMA transfer from the `0x90xxxxxx` mirror range will result in a bus error [cite: Volume XVI: DMA Controller].

## 3. SRAM Cave Isolation & Stub Collision

The RAM Cave (`0x4000807A`) resides in internal SRAM, which is physically isolated from the SDRAM buffers [cite: Volume VI: Addendum]. This isolation allows the hybrid payload to remain active while the firmware is being flashed [cite: Volume XIX: Revised Safety].

### The Flasher Stub Collision

While isolated from SDRAM, the RAM Cave shares SRAM with the Flash Programming Stub (uploaded during Stage 3 & 4 of the flasher) [cite: gcc_hitachi_flasher.c].

- SRAM Capacity: ~36,604 Bytes [cite: Volume VI: Memory & Buffer Map].
- Collision Threshold: If the hybrid payload grows beyond 3,634 bytes, it will physically collide with the 4,080-byte Flasher Stub [cite: Volume VI: Memory & Buffer Map, gcc_hitachi_flasher.c]. This collision triggers a crash during the Ignition phase [cite: Volume XIX: Revised Safety].